1. Field of the Invention
The present disclosure generally relates to the field of integrated circuits, and, more particularly, to thermal management and monitoring of thermally induced stress forces of semiconductor devices.
2. Description of the Related Art
In modern integrated circuits, a very high number of individual circuit elements, such as field effect transistors in the form of CMOS, NMOS, PMOS elements, resistors, capacitors and the like, are formed on a single chip area. Typically, feature sizes of these circuit elements are continuously decreased with the introduction of every new circuit generation, to provide currently available integrated circuits formed by volume production techniques with critical dimensions of 50 nm or less and having an improved degree of performance in terms of speed and/or power consumption. A reduction in size of transistors is an important aspect in steadily improving device performance of complex integrated circuits, such as CPUs. The reduction in size is commonly associated with an increased switching speed, thereby enhancing signal processing performance at transistor level.
Due to the decreased dimensions of the active circuit elements, not only the performance of the individual transistor elements may be increased, but also their packing density may be improved, thereby providing the potential for incorporating increased functionality into a given chip area. For this reason, highly complex circuits have been developed, which may include different types of circuits, such as analog circuits, digital circuits and the like, thereby providing entire systems on a single chip (SoC).
The increased packing density of integrated circuits resulting from the reduced device dimensions may also be accompanied by reduced switching speeds of the individual transistors in complex logic circuitry, thereby, however, contributing to increased power consumption in MOS circuits, since the reduced switching speeds allow the operation of the transistors at higher switching frequencies, which in turn increases the power consumption of the entire device. Therefore, in sophisticated applications using densely packed integrated circuits, the heat generation may reach extremely high values due to the dynamic losses caused by the high operating frequency, in combination with a significant static power consumption of highly scaled transistor devices owing to increased leakage currents that may stem from extremely thin gate dielectrics, short channel effects and the like. Therefore, great efforts are being made in order to reduce overall power consumption by restricting the usage of high performance transistors, which usually cause higher heat generation, to performance critical signal paths in the circuit design, while using less critical devices in other circuit areas. Moreover, appropriate mechanisms may be implemented to operate certain circuit portions “on demand” and control local or global operating conditions depending on the thermal situation in the semiconductor die.
The heat generated during the operation of the internal circuit elements is typically dissipated via the substrate material and the complex metallization system including highly conductive metals and sophisticated dielectric materials, depending on the overall configuration of the semiconductor device, the package accommodating the semiconductor device and the contact regime for connecting the metallization system to the wiring system of the package. Finally, the internally generated heat has to be transferred to the package and to an external cooling system connected to the package. Thus, a wide variety of cooling systems, with complex passive architectures, such as specifically designed heat sinks and heat pipes, and also expensive active cooling devices, for instance in the form of fans, water cooling systems, Peltier elements and the like, are used. With the quest for high performance of complex semiconductor devices, the corresponding power consumption of semiconductor devices, such as microprocessors, have reached the 100 Watt range, while the shrinking technology ground rules have resulted in increased thermal density of these semiconductor devices, as more transistors are packed into a smaller die region. External heat management systems, e.g., systems which may be operated on the basis of the internal thermal state of the semiconductor device, may not permit a reliable estimation of the die internal temperature distribution due to the delayed thermal response of the package of the semiconductor device and the possibly insufficient spatial temperature resolution of device internal temperature monitoring systems. Accordingly, external cooling systems may have to be designed so as to take into consideration these restrictions and to provide sufficient operational margins with respect to heat control unless a certain risk of overheating and thus possibly damaging specific critical circuit portions may be caused.
Consequently, a plurality of test strategies have been developed in order to determine or predict the temperature distribution in complex semiconductor chips in order to reliably identify temperature critical regions. It turns out, however, that the identification of hot spots in a complex integrated circuit may be difficult on the basis of the layout of the device so that frequently appropriate temperature sensing systems may not provide a reliable mesh of temperature values, as discussed above. For this reason, frequently, specific test algorithms may be performed, for instance, by power cycling a device under consideration in order to determine the thermal stress of the device under well-defined conditions. For example, a packaged semiconductor device may be operated in a well-defined manner, i.e., by running specific routines or applications, such as booting an operating system and the like, wherein any such applications may be selected so as to simulate the real world situation of the semiconductor device when used in any technical application. The temperature data may be obtained on the basis of the device-internal temperature sensors which, as discussed above, may not reliably represent the actual temperature distribution in the device. Furthermore, the selected mode of operation of the device under test may not necessarily represent the worst case situation during actual technical applications, thereby also reducing the authenticity and thus reliability of the correspondingly obtained measurement data.
In recent developments, semiconductor chips and package substrates may increasingly be directly attached to each other, which may be accomplished by providing an appropriate contact structure above the last metallization layer of the metallization system of the semiconductor chip and providing a complementary structure on the package substrate. In this manner, a large number of electrical or thermal contacts may be established across the entire area of the semiconductor chip, thereby significantly enhancing electrical and thermal performance of the packaged semiconductor device. That is, due to the direct contact of the complementary contact structures of the chip and the package, a large number of low resistance and low capacitive electrical connections may be established compared to, for instance, wire bond techniques, wherein at the same time the entire chip area is available for providing the contacts, contrary to wire bond techniques in which the bond pads are essentially restricted to the edge of the semiconductor chip. Although this direct contact regime between the package and the semiconductor chip may provide significant advantages and thus has resulted in a growing trend to apply this contact regime, in particular in cases in which increased I/O (input/output) capabilities are required. Additional difficulties may arise, in particular when further reducing the overall dimensions of the circuit features, which may also result in a reduction of the lateral size of the contact elements, for instance provided in the form of solder bumps, metal pillars and the like.
In sophisticated semiconductor devices, the overall signal propagation delay may no longer be limited by the individual semiconductor-based circuit elements but may be restricted by the electrical performance of the complex metallization system. That is, due to the ongoing shrinkage of the critical dimensions of the transistors, thereby providing advanced semiconductor devices having field effect transistors with a gate length of 50 nm and less, the metallization systems also require reduced metal lines, which may typically result in increased current densities. For this reason, increasingly, copper, copper alloys and the like may be used in order to replace aluminum in order to take advantage of copper's superior characteristics in terms of conductivity and electromigration behavior. It is well known that copper has a higher conductivity and also suffers from less electromigration compared to aluminum, thereby enabling a reduction of the cross-sectional areas of corresponding metal lines. Upon reducing the dimensions of the metal lines, also the pitch between neighboring metal lines has to be reduced, which in turn results in an increase of the parasitic capacitance. Therefore, new dielectric materials are increasingly replacing the well-established dielectric materials, such as silicon dioxide and silicon nitride, in order to reduce the overall dielectric constant in the metallization system. The reduced dielectric constant is typically accomplished by reducing the density of the dielectric materials, for instance by providing a porous structure and the like, which in turn, however, is typically accompanied by inferior mechanical characteristics. For example, such low-k dielectric materials may be more brittle compared to, for instance, silicon dioxide, while also generally the mechanical strength is reduced for these materials. In direct contact regimes (flip-chip), as discussed above, however, the package and the semiconductor chip, i.e., the metallization system thereof, are directly connected via the contact structure so that any mechanical stress caused in the package and/or the semiconductor chip may be transferred more efficiently into the other component. It is well known that usually used package substrates may have a significantly different coefficient of thermal expansion (CET) compared to the semiconductor material. Consequently, the thermal expansion of the components may be adapted for a narrow width of temperatures only, and the temperature below or above a specified temperature range may result in a significant difference in the thermal expansion, which in turn may result in significant mechanical stress forces resulting in a certain degree of bending or bowing of the package substrate. Due to the direct mechanical coupling via the contact structures of the semiconductor chip and the package substrate, any thermally induced mechanical stress forces may be “efficiently” transferred into the metallization system, which may thus have to act as a buffer material for accommodating the different thermal expansion behaviors between the package and the semiconductor chip. Due to the very different mechanical characteristics of the sophisticated low-k dielectric materials, the resulting shear forces occurring in the metallization system may result in significant damage, such as delamination of dielectric layers, the formation of cracks and the like. This situation became even worse in most recent developments in which a lead-free contact regime is to be applied, for instance in view of legal regulations and the like. As is well known, typical lead-containing solder materials, which are frequently used in a direct contact regime in the form of solder balls, may have a certain degree of resiliency, thereby accommodating a certain amount of the difference between the different thermal expansion behaviors. On the other hand, lead-free solder materials may be significantly stiffer, thereby resulting in a direct transfer of the resulting stress forces into the sensitive metallization system. In other cases, the lateral distance between the package substrate and the metallization system, i.e., the height of the corresponding contact elements, may be reduced, for instance by providing metal pillars and the like, which are typically comprised of copper, possibly in combination with a lead-free solder material, thereby even further enhancing the resulting stiffness of the contact element, which in turn leads to even more pronounced mechanical stress forces in the metallization system. It has been recognized that, in particular, pronounced mechanical stress may be observed at the edge of the semiconductor chip, for instance caused by the solder process upon connecting the package substrate and the semiconductor chip, thereby generating a weak spot of the metallization system, which may typically not be considered as a critical area when examined in view of the thermal stress of a semiconductor chip.
For this reason, it is important to identify any weak spots of the metallization system which may be caused by mechanical stress forces, while at the same time taking into consideration the thermal stress, which significantly influences the mechanical stress in a complex metallization system due to the pronounced chip-package interaction. In conventional monitoring strategies, however, reliability tests for packaged semiconductor devices may typically be performed on the basis of test structures in which the thermal load may be used from external sources with a temperature distribution that is evenly applied across the semiconductor chip. Consequently, corresponding failure mechanisms detected on the basis of these test structures may not reliably reflect the actual situation in the packaged semiconductor device so that reliable predictions about the operational behavior of a corresponding semiconductor device are difficult to achieve on the basis of these conventional strategies.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.